A LOCOS (local oxidation of silicon) process has been developed and widely used as a semiconductor device isolation technology. As the LOCOS process has generally been used, new device isolation technologies have been developed to address shortcomings of the LOCOS process. For example, PBL (poly buffer LOCOS) and R-LOCOS (Recessed LOCOS) are widely used. However, these technologies have shortcomings in the context of high-integration of semiconductor devices. For instance, they are complicated processes and cannot fundamentally overcome problems such as bird's beak, which is produced as a result of the lifting of the edges of a nitride layer during subsequent oxidation. Moreover, a planarization process must be carried out after the completion of the LOCOS process because of the level difference between active regions and field regions.
To address the problems of the conventional device isolation technologies, a shallow trench isolation (hereinafter referred to as “STI”) process has been developed. The STI process achieves good device isolation characteristics and is suitable for the high-integration of semiconductor devices because the STI structure occupies a small area.
A prior art STI process comprises: forming a trench within a field region of a semiconductor substrate, filling the trench with an oxide layer through a gap filling process, and planarizing the resulting semiconductor substrate by using a chemical mechanical polishing (hereinafter referred to as “CMP”) process. The oxide layer to gap-fill the trench is preferably an O3-TEOS (tetra-ethyl-ortho-silicate) layer formed by using APCVD (atmospheric pressure chemical vapor deposition). The oxide layer may be created by HDP CVD (high density plasma chemical vapor deposition).
Sekikawa et al., U.S. Pat. No. 6,489,661, describes a method of forming an element isolation film using LOCOS technology. The Sekikawa et al. Patent uses a pad oxidation film and a pad poly-Si film as an underlying buffer layer of an oxidation resisting film. The pad oxidation film and the pad poly-Si film are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film.
Jang et al., U.S. Pat. No. 6,153,481, describes a method of forming an element isolation insulating film of a semiconductor device by employing a PBL method to reduce the bird's beak and to increase the length of the effective active region. The Jang et al. Patent comprises: sequentially forming a pad-oxide film, a stack-silicon film, and a nitride film on a semiconductor substrate; forming an element isolation region by selectively patterning the nitride film with an etching process by using an element isolation mask; and forming an element isolation film by field-oxidizing the element isolation region over the semiconductor substrate.
Sun et al., U.S. Pat. No. 5,612,249, describes a method of defining a LOCOS field isolation process after a poly gate is deposited. The Sun et al. Patent comprises: growing a gate oxide on a silicon substrate; depositing poly or amorphous silicon, depositing a thin layer of PECVD or LPCVD oxide on the poly or amorphous silicon, depositing LPCVD nitride as a hard mask, and defining a device active area by using a photoresist mask and performing a plasma etch.
FIGS. 1a and 1b are cross-sectional views illustrating a conventional STI process. Referring to FIG. 1a, a sacrificial layer is formed over the entire surface of a semiconductor substrate 101. The sacrificial layer preferably consists of an oxide layer 102 and a nitride layer 103. At least one opening is formed through the nitride layer 103 and the oxide layer 102 on a field region of the semiconductor substrate 101 by performing a photolithography process. At least one trench is then formed within the field region of the semiconductor substrate 101 by using the nitride layer 103 as an etching mask. An oxide layer 104 is grown along the sidewalls and bottom of the trench(es) 105. The trench(es) are then filled with an insulating layer 105 having good gap-fill characteristics. The insulating layer 105 may be, for example, oxide. Next, a planarization process is performed on the resulting structure.
Referring to FIG. 1b, the nitride layer 103 is etched by a phosphoric acid solution to expose the oxide layer 102. The oxide layer 102 is then etched by an HF solution to expose the surface of the active region of the semiconductor substrate 101. This completes the STI process.
The conventional STI process of FIGS. 1a-1b must remove some portion(s) of the insulating layer 105 through an etching process in order to lower the insulating layer 105 in height compared to the nitride layer 103 after the completion of the planarization process. During this process, the area of the insulating layer 105 which is in contact with the nitride layer 103 is etched more rapidly than the other parts of the insulating layer 105. Thus, after the nitride layer 103 and the oxide layer 102 are etched to expose the surface of the active region of the semiconductor substrate 101, as shown in FIG. 1b, a divot 106 on the upper edge of the trench is deepened. The deepened divot 106 may increase leakage current on the upper edge of the trench.
The above-described STI process may also increase costs as compared to the existing LOCOS process due to the complicated process and the change of the process margin due to the CMP process.